Increasing the density of integrated circuits, maximizing performance and lowering costs are ongoing goals of the electronic industry. In particular, portable systems and computers have spurred the efforts to define reliable packaging technologies for supplying circuits in the smallest possible area, and in many applications with increased operating speed.
Advances in interconnect technology have provided the key enablers toward these ends. Direct connection of the active surface of a semiconductor die to a substrate or package using solder balls for flip-chip attachment, furnished the basic technology for low inductance, area array assembly of integrated circuits, and in turn supports improved overall switching speed. Flip-chip technology was developed years ago, and has surged recently as more practical means of direct chip attach have evolved, and begun to replace wire bonding. The early technique of forming solder balls by evaporating, patterning and reflowing solders on semiconductor wafers as a means to make contact between the input/output pads on the chip and the substrate is being replaced. Techniques, such as plating solders or other metallic bumps, using solder or conductive polymers to adhere conductive spheres, or using conductive polymers or anisotropic conductive materials have been developed for direct attachment and electrical contact between chips and a substrate.
Not only are chips attached to substrates by direct chip attach, but packages such as ball grid array (BGA), chip scale packages (CSP), and board-on-chip (BOC) packages are attached to circuit boards or other second level interconnection by means of balls or bumps. These bump connected packages are beginning to replace leaded packages which require more circuit board area and have higher inductance. Ball sizes vary from those in the range of 75 microns used for flip-chip attachment to those greater than a millimeter in diameter for CSP and BGA attachment. FIG. 1A provides a cross sectional view of a flip-chip 105 assembly in a BGA package 106, and demonstrates the use of different ball sizes, i.e. solder balls 115 on the flip-chip assembly typically yield a stand off height of about 65 microns, whereas balls 116 on the BGA package have about 0.9 mm stand off.
Device performance is enhanced by the lower inductance of short, wide ball connections, as a replacement for long, thin wire bonds or lead conductors. These bumped devices may also have terminals in an array under the device, rather than at the perimeter, and thereby minimize conductor length. Substrate space is reduced by placing the terminals within the active area, and thereby supports increased packing density.
FIG. 1B shows a cross-sectional view of a BOC package which includes a thin, rigid printed wiring board 110 to which the active surface of the integrated circuit 111 is attached on one surface of the board by a tape 113 with adhesive on both sides, and ball connections 112 for contact to the second level of interconnection are placed on the opposite side of the board. The integrated circuit is electrically connected to the substrate board by wire bonds 114 or by direct chip attachment, and the contact area is protected by a polymeric potting 120 or molding compound. BOC packages are one of many forms of Chip Scale Packages (CSP), and may be very thin as a result of the printed wiring board thickness.
Often in order to make an electronic device functional, one or more integrated circuit chips may be coupled electronically, and conveniently the chips are positioned next to each other and are connected by circuitry on a circuit board. Multichip modules provide a means for fabricating subsystems by interconnecting chips on a common substrate or package. FIG. 2 demonstrates an example of such an assemblage wherein a die 201 may be connected by flip-chip terminals 202, or by wire bonds 203 to the substrate. The substrate 211 provides the interconnection both between the chips within the assembly, and to external contacts 230 which in turn will contact the second level of interconnection, such as a printed wiring board 220. In multichip assemblies interconnections between chips often provides a means for decreasing the total number of input/output pins on the module, as compared to the number required for individual components. Fewer input/output interconnections to the second level printed circuit board reduces area required for interconnections, and allows performance to be enhanced by shorter interconnections with lower inductance.
Common power and ground lines further decrease the input/outputs requirements and provide enhanced performance; multichip modules frequently have multilevel substrates to satisfy this need.
Another technique for increasing density of integrated circuit devices has been stacked packages and/or stacked chips. Two or more integrated circuit chips are stacked on top of each other, and in the conventional arrangement all chips face the same direction, i.e., downward, upward or side by side. A common example is Memory modules, either as chips or packaged units having similar size and type which are stacked face-to-back and are electrically interconnected vertically on the perimeter.
Leaded surface mount packages on double sided printed wiring boards were a forerunner of face-to-face stacked packages. Chips have also been stacked face-to-face on an interposer. One such assembly, shown in FIG. 3 provides a first flip-chip 301 positioned face-to-face with a second flip-chip 302 on an interposer 303 between the chips to provide electrical connection 313 among the flip-chip terminals 311, and to external circuitry terminal 315. This assembly uses a flex circuit as the interposer 303 between the facing flip-chips, and thus requires a separate mechanical support 320 to provide the interconnection between the interposer and a second level interconnection. This results in a complex and costly assembly. Moreover, the package height is increased by this arrangement.
It would be advantageous to develop a technique for increasing the packing density of integrated circuits, taking advantage of low inductance connectors, decreasing the number of input/output contacts as is found with multichip or stacked assembly, and makes use of low cost, readily available assembly materials for packaging. In particular, there is a need for increasing the density of memory circuits used in computers on SIMMs (single inline memory module) or circuit boards. This application must comprehend not only the area restrictions, but also the package height. Memory module applications would like to take advantage of the ability to double the memory capacity by stacking chips, but suffer no penalty in the space allotted for memory modules.